XC2S30-5TQG144C

SPARTAN-II, FPGA, 30K, 144-TQFP, 2.5V , –0.5 to 3.0 V, Second generation ASIC

Rated 5 Rating 5 | reviews | Write a review

Price:: US $9.00~10.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $9.00~10.00

PartNumber:: XC2S30-5TQG144C

Brand:: Xilinx, Inc - Xilinx | Pack: DIP | D/C: 11+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Joy's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-12-29

From Other Seller

Part Number:XC2S30-5TQG144C
US $9.00 - 10.00
ECA1HHG220

US $2.00 - 10.00 / Piece
(0) Remove
LM64P101

US $240.00 - 300.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The XC2S30-5TQG144C is a Spartan-II Field-Programmable Gate Array. It gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The XC2S30-5TQG144C offers densities ranging from 50,000 to 600,000 system gates. System performance is supported beyond 200 MHz.

Parametrics

XC2S30-5TQG144C absolute maximum ratings: (1)Supply voltage relative to GND:–0.5 to 3.0 V; (2)Supply voltage relative to GND:–0.5 to 4.0 V; (3)Input reference voltage: –0.5 to 3.6 V; (4)Input voltage relative to GND: 5V tolerant I/O(4), –0.5 to 5.5 V; No 5V tolerance(5),–0.5 to VCCO+0.5 V; (5)Voltage applied to 3-state output: 5V tolerant I/O,–0.5 to 5.5 V; No 5V tolerance,–0.5 to VCCO +0.5 V; (6)Storage temperature (ambient): –65 to +150 ℃; (7)Junction temperature: +125 ℃.

Features

XC2S30-5TQG144C features:(1)Second generation ASIC replacement technology; (2)Fully PCI compliant; (3)Low-power segmented routing architecture; (4)Full readback ability for verification/observability; (5)Dedicated carry logic for high-speed arithmetic; (6)Efficient multiplier support; (7)Cascade chain for wide-input functions; (8)Abundant registers/latches with enable, set, reset; (9)Four dedicated DLLs for advanced clock control; (10)Four primary low-skew global clock distribution nets; (11)IEEE 1149.1 compatible boundary scan logic; (12)Versatile I/O and packaging; (13)Core logic powered at 2.5V and I/Os powered at 1.5V, 2.5V, or 3.3V; (14)Fully supported by powerful Xilinx ISE development system.